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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MPC17517 Rev 1.0, 03/2004
Advance Information 1.0 A 6.8 V Dual Motor Driver IC
The 17517 is a monolithic triple totem-pole-output power IC designed to be used in portable electronic applications to control small DC motors and solenoids. The 17517 can operate efficiently with supply voltages as low as 2.0 V to as high as 6.8 V. Its low RDS(ON) totem-pole output MOSFETs (0.46 typical) can provide continuos drive currents of 1.0 A and handle peak currents up to 3.0 A. It is easily interfaced to low-cost MCUs via parallel 3.0 V- or 5.0 Vcompatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz.
17517
1.0 A 6.8 V DUAL MOTOR DRIVER IC
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The 17517 can drive two motors in two directions one at a time or drive one motor in two directions and one solenoid with synchronous rectification of freewheeling currents one at a time. Two-motor operation is accomplished by hooking one motor between OUTA and OUTB and hooking the other motor between OUTB and OUTC. Motor plus solenoid operation is accomplished by hooking a motor between OUTA and OUTB and a solenoid between OUTC and GND. This device contains an integrated charge pump and level shifter (for gate drive voltages), integrated shoot-through current protection (cross-conduction suppression logic and timing), and undervoltage detection and shutdown circuitry. The 17517 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). Features * 2.0 V to 6.8 V Continuous Operation * Output Current 1.0 A (DC), 3.0 A (Peak) * MOSFETs < 600 m RDS(ON) @ 25C Guaranteed * 3.0 V/5.0 V TTL-/CMOS-Compatible Inputs * PWM Frequencies up to 200 kHz * Undervoltage Shutdown
DTB SUFFIX CASE 948F-01 16-LEAD TSSOP
ORDERING INFORMATION
Device MPC17517DTB/R2 Temperature Range (TA) -20C to 65C Package 16 TSSOP
Simplified Application Diagram 17517 Simplified Application Diagram
5.0 V 17517 VDD C1L C1H C2L C2H CRES EN1 EN2 IN1 IN2
5.0 V VM OUTC
OUTA
Solenoid MOTOR
MCU
OUTB GND
This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2004
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C2L
Charge Pump
C2H
C1H LowVoltage Shutdown CRES
C1L
VM
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VDD OUTC
IN1
Level Shifter Predriver
OUTB
IN2 Control Logic EN1
OUTA
EN2
GND
Figure 1. 17517 Simplified Internal Block Diagram
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VDD
VM OUTA CRES C2H C2L IN1 IN2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
OUTC GND OUTB VM C1H C1L EN2 EN1
TERMINAL FUNCTION DESCRIPTION
Terminal Terminal Name VDD VM OUTA CRES C2H C2L IN1 IN2 EN1 EN2 C1L C1H OUTB GND OUTC Formal Name Control Circuit Power Supply Motor Drive Power Supply Output A Charge Pump Output Capacitor Connection Charge Pump 2H Charge Pump 2L Input Control 1 Input Control 2 Enable Control Signal Input 1 Enable Control Signal Input 2 Charge Pump 1L Charge Pump 1H Output B Ground Output C Definition Positive power source connection for control circuit. Motor power supply voltage input terminals. Driver output A terminal. Charge pump reservoir capacitor terminal. Charge pump bucket capacitor 2 (positive pole). Charge pump bucket capacitor 2 (negative pole). Control signal input 1 terminal. Control signal input 2 terminal. Enable control signal input 1 terminal. Enable control signal input 2 terminal. Charge pump bucket capacitor 1 (negative pole). Charge pump bucket capacitor 1 (positive pole). Driver output B terminal. Ground connection. Driver output C terminal.
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1 2, 13 3 4 5 6 7 8 9 10 11 12 14 15 16
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to the device.
Rating Motor Supply Voltage Charge Pump Output Voltage Logic Supply Voltage Signal Input Voltage Driver Output Current Continuous Peak (Note 1) IO IOPK VESD1 VESD2 TSTG TJ TA RJA PD TSOLDER 1.0 3.0 V 2000 100 -65 to 150 -20 to 150 -20 to 65 190 657 245 C C C C/W mW C Symbol VM Value -0.5 to 8.0 -0.5 to 14 -0.5 to 7.0 -0.5 to VDD +0.5 Unit V V V V A
V
CRES
VDD VIN
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ESD Voltage Human Body Model (Note 2) Machine Model (Note 3) Storage Temperature Range Operating Junction Temperature Operating Ambient Temperature Thermal Resistance (Note 4) Power Dissipation (Note 5) Soldering Temperature (Note 6) Notes 1. TA = 25C, 10 ms pulse width at 200 ms intervals. 2. 3. 4. 5. 6. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 37 mm x 50 mm Cu area (1.6 mm FR-4 PCB). Maximum at TA = 25C.
Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions TA = 25C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER
Motor Supply Voltage Logic Supply Voltage Capacitor for Charge Pump Standby Power Supply Current Motor Supply Standby Current IV I
MSTBY
VM VDD C1, C2, C3
2.0 2.7 0.01
5.0 5.0 0.1
6.8 5.7 1.0
V V F
- -
- -
1.0 1.0
A mA mA
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Logic Supply Standby Current (Note 7) Operating Power Supply Current Logic Supply Current (Note 8) Charge Pump Circuit Supply Current Low-Voltage Detection Circuit Detection Voltage (VDD) (Note 9) Driver Output ON Resistance (Note 10)
VDDSTBY I I
VDD
- -
- -
3.0 0.7 V
CRES
VDDDET 1.5 RDS(ON) - 2.0 0.46 2.5 0.60
GATE DRIVE
Gate Drive Voltage (Note 11) No Current Load Gate Drive Ability (Internally Supplied) IC
RES = -1.0 mA
VC RES
V
V 12 10 13 11.2 13.5 V -
CRESload
CONTROL LOGIC
Logic Input Voltage Logic Input Function (2.7 V < VDD < 5.7 V) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Notes 7. 8. 9. 10. 11. I I VDDSTBY includes current to the predriver circuit. VDD includes current to the predriver circuit. VIN VIH VIL IIH IIL 0 VDD x0.7 - - -1.0 - - - - - VDD - VDD x0.3 1.0 - V V V A A
Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the gate V V voltage CRES is applied from an external source, CRES = 7.5 V. IO = 1.0 A source + sink. Input logic signal not present.
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DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions TA = 25C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
INPUT (IN1, IN2, EN1, EN2)
Pulse Input Frequency Input Pulse Rise Time (Note 12) Input Pulse Fall Time (Note 14) fIN tR tF - - - - - - 200 1.0 (Note 13) 1.0 (Note 13) kHz s s
OUTPUT
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Propagation Delay Time Turn-ON Time Turn-OFF Time Charge Pump Wake-Up Time (Note 15) Low-Voltage Detection Time Notes 12. 13. 14. 15. tPLH tPHL tVGON - - - - 0.1 0.1 0.1 - 0.5 0.5 3.0 10
s
ms ms
tV
DDDET
Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. When C1 = C2 = C3 = 0.1 F.
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Timing Diagrams
VDD 50%
IN1, IN2, EN1, EN2
tPLH
OUTA, OUTB, OUTC 90% 10%
tPHL
t VGON
V
11 V
CRES
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Figure 2. tPLH, tPHL, and tPZH Timing
Figure 4. Charge Pump Timing
VDDDETon VDD 0.8 V/ 1.5 V
2.5 V/3.5 V 50%
VDDDEToff
tV
DDDET
tV
90%
DDDET
IM
0% (<1.0 A)
Figure 3. Low-Voltage Detection Timing
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Table 1. Truth Table
INPUT IN1 Shutdown Mode X X L L Z Z Z IN2 EN1 EN2 OUTA OUTPUT OUTB OUTC
Channel 1 (A-B) Driving Mode H H L L H L H L H H H H L L L L L H L Z L L H Z Z Z Z Z
Channel 2 (B-C) Driving Mode
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H H L L
H L H L
L L L L
H H H H
Z Z Z Z
L H L Z
L L H Z
Half-Bridge (C) Driving Mode H H L L H = High. L = Low. Z = High impedance. X = Don't care. H L H L H H H H H H H H Z Z Z Z Z Z Z Z Z H L Z
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 17517 is a triple totem-pole output H-Bridge power IC designed to drive small dc motors used in portable electronics. The 17517 can operate efficiently with supply voltages as low as 2.0 V to as high as 6.8 V, and provide continuos motor drive currents of 1.0 A while handling peak currents up to 3.0 A. It is easily interfaced to low cost MCUs via parallel 3.0 V- or 5.0 Vcompatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz. The 17517 can drive two motors in two directions one at a time; or it can drive one motor in two directions and one solenoid with synchronous rectification of freewheeling currents one at a time. Two-motor operation is accomplished by hooking one motor between OUTA and OUTB, and the other motor between OUTB and OUTC. Motor + solenoid operation is accomplished by hooking a motor between OUTA and OUTB and placing a solenoid between OUTC and GND. Table 1, Truth Table, page 8, describes the operating states versus the input conditions. As shown in Figure 1, 17517 Simplified Internal Block Diagram, page 2, the 17517 is a monolithic triple totem-pole output bridge with built-in charge pump circuitry. Each of the six MOSFETs forming the triple totem-pole output has an RDS(ON) of 0.6 (guaranteed by design). The IC has an integrated charge pump and level shifter (for gate drive voltages). Additionally, the IC has a built-in shoot-through current protection circuit and undervoltage lockout function. This IC has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance).
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FUNCTIONAL TERMINAL DESCRIPTION OUTA, OUTB, and OUTC
These terminals provide the connection to the internal power MOSFET triple-totem-pole H-bridge of the IC. The VM terminals must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between terminals.
GND
Power and signal ground terminal.
IN1, IN1, EN1, and EN2
These terminals are input control terminals used to control the outputs. These terminals are 3.0 V/5.0 V CMOS-compatible inputs with hysteresis. These terminals work together to control OUTA, OUTB, and OUTC (refer to Table 1, Truth Table).
CRES
This terminal provides the connection for the external reservoir capacitor (output of the charge pump). Alternatively, this terminal can also be used as an input to supply gate-drive voltage from an external source via a series current-limiting resistor. The voltage at the CRES terminal will be approximately three times the VDD voltage, as the internal charge pump utilizes a voltage tripler circuit. The VDDRES voltage is used by the IC to supply gate drive for the internal power MOSFETs.
C1L and C1H, C2L and C2H
These two pairs of terminals, the C1L and C1H and the C2L and C2H, connect to the external bucket capacitors required by the internal charge pump. The typical value for the bucket capacitors is 0.1 F.
VDD
This terminal carries the logic supply voltage and current into the logic sections of the IC. VDD has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input terminals.
VM
The two VM terminals carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and/or modulated by the IC as it delivers the power to the load attached between OUTA and OUTB.
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APPLICATIONS Typical Application
Figure 5 shows a typical application for the 17517. When applying the gate voltage to the CRES terminal from an external source, be sure to connect it via a resistor equal to, or greater than, R = VC /0.02 .
G
RES
5.0 V 17517
V
CRES < 14 V RG > CRES /0.02
V
NC NC NC NC
0.01 F
C1L C1H C2L C2H CRES
VDD
VM
OUTA
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RG
OUTB
MCU
EN1 EN2 IN1 IN1
OUTC
GND
NC = No Connect
Figure 5. 17517 Typical Application Diagram
CEMF Snubbing Techniques
Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads. Typical practice is to provide snubbing of voltage transients by placing a capacitor or zener at the supply terminal (VM) (see Figure 6).
5.0 V 5.0 V 17517 VDD VM C1L C1H C2L C2H CRES OUT 5.0 V 5.0 V 17517 VDD VM C1L C1H C2L C2H CRES OUT
PCB Layout
When designing the printed circuit board (pcb), connect sufficient capacitance between power supply and ground terminals to ensure proper filtering from transients. For all highcurrent paths, use wide copper traces and shortest possible distances.
OUT
OUT
GND
GND
Figure 6. CEMF Snubbing Techniques
17517 10
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PACKAGE DIMENSIONS
DTB SUFFIX 16-LEAD TSSOP PLASTIC PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8
2X
L/2
J1 B -USECTION N-N J
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L
PIN 1 IDENT. 1 8
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -VN F DETAIL E
C 0.10 (0.004) -TSEATING PLANE
-W-
D
G
H
DETAIL E
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